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Digital Design Engineer

Company: Codelucida Inc.
Location: Tucson
Posted on: November 22, 2021

Job Description:

We're seeking a skilled hardware design Engineer having knowledge and expertise in digital design for both ASIC and FPGA ,with a specific emphasis on all aspects of the ASIC design flow from front-end design to pre-silicon validation. Past experience in developing and integrating IP cores into SoC/chips is desirable.The main responsibility of the candidate will be developing new RTL designs as well as reviewing existing RTL designs and identifying areas of improvement to improve timing or power usage. The candidate will also be in charge of testing and verification of the designs based on industry best practices, and finally of transforming the designs into suitable packages for delivery to customers/strategic partners.Competitive compensation will be provided including startup equity along with standard health insurance benefits.Specific tasks that the position will involve (but not limited to) areFront-end Design:AUnderstanding and review of existing RTL design methodologies used by company in the implementation of its current error-correction algorithms. Identifying areas of improvement w.r.t. timing, power, routing, taking into account effects on back-end design. Primary tool expected to be used is Synopsys DC-G.Testing and Verification:ADeveloping appropriate debugging modules for adequate testing of the RTL designs. Hand-on simulation of the RTL designs using appropriate tools such as Synopsys VCS. Performing timing and power analysis with Prime Time and Prime Time PX. Generating PPA (Performance/Power/Area) reports for various RTL designs. Efficient functional verification of the RTL designs on FPGA.Back-end Design Support:AFamiliarity with floor planning, place-and-route to optimize its impact on timing and power, and work in conjunction with third-party back-end design contractors utilized by the company to address any issues including proposing modifications on the front-end design.AIP Packaging and Integration:ADeveloping packages to accompany the RTL designs including test modules, C/C++ and/or python simulators and wrappers to bring the overall IP in a suitable format to support IP integration with customers and strategic partners.Design Documentation:APreparing design documentation and manuals to support the deliverable IP cores.SKILLS REQUIREDDesirable experience in the hardware design industry involved in ASIC/SoC design with strong background on front-end design.Strong VHDL skills preferred with experience in SystemVerilogKnowledge in all aspects of ASIC design flow including Synthesis, verification and rule check, place-and-route, timing closure, static and dynamic power analysis, etc.AProficiency in python, TCL scriptsProficiency and experience using front-end Synopsys Design toolsExperience in Synopsys VCS, PT, PTPXExperience in pre-silicon verification with familiarity in post-silicon validation.by Jobble

Keywords: Codelucida Inc., Tucson , Digital Design Engineer, Engineering , Tucson, Arizona

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