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Engineering Fellow - FPGA/ASIC Design

Company: Raytheon Missiles & Defense
Location: Tucson
Posted on: November 26, 2022

Job Description:

About Us:

At Raytheon Missiles & Defense, you have the opportunity to try new things and make a bigger difference across a broader end-to-end solution, a richer technology and product set, an expanded range of disciplines, a growing global footprint and a more diverse team of colleagues and customers.

Job Summary:

Raytheon Missiles and Defense is seeking technical leaders that are passionate about the design and application of configurable logic technologies to the development of world-class defense solutions. RMD is seeking an Engineering Fellow (EF) to help expand the capabilities, quality, and proficiency of Configurable Logic (CL) design within RMD and the company as a whole. This position requires an established depth of expertise in configurable logic design and verification, with a complimentary breadth of experience in adjacent disciplines: electronics design, software design, systems engineering, and signal processing.

The candidate shall have demonstrated leadership and visionary thinking in the design and development of advanced electronic systems based on configurable logic technologies. The EF candidate shall demonstrate a high degree of creativity, and ingenuity, in the design of ASICs, FPGAs, and complex heterogeneous processing systems, as well as in the application of advanced verification techniques with an emphasis on the Universal Verification Methodology (UVM), and the creation of new processes to improve the quality of all designs and the proficiency with which they are created. The candidate shall be able to perform in multi-disciplined environments to solve system level problems. The candidate shall similarly be able to drive to identify root cause and formulate solutions to complex failure investigations.

Responsibilities to Anticipate:

The Engineering Fellow will be expected to support multiple programs in the proposal, architecture and design phases to insure the optimal application of configurable logic technologies, coordinating efforts across design disciplines, and organizational boundaries. This coordination will include the oversight of those designs through formal and informal reviews, the application of model-based engineering, and process improvements. The Engineering Fellow will be a focal point for CL design expertise, often relied upon by programs to provide specific complex solutions and analysis, as well as having a broad responsibility to help define technology road maps, propose IRAD projects and set functional priorities to realize those road maps. In addition to advancing the state of the art in CL design and processes, the Engineering Fellow is expected to distribute their expertise through formal and informal mentoring, reviews, educational presentations, and wiki articles.

Qualifications You Must Have:

  • Bachelor of Science in Computer or Electrical Engineering with a minimum of 12 years of relevant experience.
  • A strong and extensive depth of knowledge in configurable logic technologies, which may include: Vendor tools and technology from Xilinx, Altera, & Microsemi, Software/Hardware languages (C, C , VHDL, UVM & System Verilog, Python), comprehensive knowledge of CL design flow, including CM, Simulation, Synthesis, P&R, script languages, verification, and/or integration.
  • Experience and depth of knowledge in the implementation of modern verification environments that include the use of constrained-random stimulus, functional coverage, code coverage, coverage collectors, scoreboards, monitors, creation of models to use through requirements to verification, and verification plans which determine the appropriate level of verification applications
  • Experience with emulation and prototyping techniques
  • Experience with and strong knowledge of industry standard interfaces and protocols such as AXI, PCIe, Ethernet, etc.
  • Experience communicating and presenting to all levels of the organization including senior level executives and external customers.
  • Experience training and mentoring others through various means including informal mentoring, reviews, presentations, publications and training.
  • Leadership experience as a project lead, team lead, technical lead or similar function with direct reports involving creating plans, schedules and cost estimates for design and verification efforts
  • Must provide evidence of patents and/or reviewed publications in applicable technical areas written / delivered within the last ten years
  • The ability to obtain and maintain a US security clearance prior to the start date. U.S. citizenship is required as only U.S. citizens are eligible for a security clearance Qualifications We Value:
    • Experience with all aspects of embedded system design and development processes
    • Have a record of Patents, Publications, and/or Technical Presentations to industry
    • Experience in space and radiation hardened design constraints, such as triple redundancy design, circumvent and recover, etc.
    • Background in RF, EO, including knowledge of the common algorithms applied to those domains.
    • Knowledge of ASIC design flow and process
    • Comprehensive knowledge of CL design tools, including CM, Simulation, Synthesis, P&R, script languages, etc.
    • Experience developing new and novel concepts leading to the capture and execution of technology maturation and development programs, transitioning into real products and deployed systems
    • Experience architecting, modeling, designing, implementing, and testing complex, heterogeneous processing systems. What We Offer:

      Whether you're just starting out on your career journey or are an experienced professional, we offer a robust total rewards package that goes above and beyond with compensation; healthcare, wellness, retirement and work/life benefits; career development and recognition programs. Some of the superior benefits we offer include parental (including paternal) leave, flexible work schedules, achievement awards, educational assistance and child/adult backup care.

      This position is located in beautiful Tucson, AZ. Tucson has a friendly, caring and laid-back atmosphere, combined with the innovation and energy of a metropolitan region and recognized as one of America's 10 Best Small Cities. Surrounded by beautiful mountains, colorful Sonoran Desert landscape and majestic saguaro cacti, Tucson is blessed with some of nature's best work. Tucson is known for its bright blue skies, and with more than 310 sunny days per year, Tucson's fantastic weather lets residents enjoy the outdoors year-round.

      Additional Details:

      Clearance Information: This position requires the eligibility to obtain a security clearance. Non-US citizens may not be eligible to obtain a security clearance. The Defense Industrial Security Clearance Office (DISCO), an agency of the Department of Defense, handles and adjudicates the security clearance process. More information about Security Clearances can be found on the US Department of State government website here:

      Employee Referral Award Eligibility: Only employees currently within RMD and RI&S have the potential to receive a Referral Award for submitting a referral to RMD and RI&S roles. ALL eligibility requirements must be met ( see guidelines ) to receive the Referral Awarding.

      Raytheon Technologies is An Equal Opportunity/Affirmative Action Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability or veteran status, age or any other federally protected class.

Keywords: Raytheon Missiles & Defense, Tucson , Engineering Fellow - FPGA/ASIC Design, Engineering , Tucson, Arizona

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